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document number: mc34713 rev. 5.0, 12/2008 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007-8. all rights reserved. 5.0 a 1.0 mhz fully integrated single switch-mode power supply the 34713 is a highly integrated, s pace efficient, low cost, single synchronous buck switching regulator with integrated n-channel power mosfets. it is a high performance point-of-load (pol) power supply with the ability to track an external reference voltage in different configurations. its high efficient 5.0 a continuous output current capability combined with its voltage tracking/s equencing ability and tight output regulation, makes it ideal as a single power supply. the 34713 offers the designer the flexibility of many control, supervisory, and protection functions to allow for easy implementation of complex designs. it is housed in a pb-free, thermally enhanced, and space-efficient 24-pin exposed pad qfn. features ?50 m integrated n-channel power mosfets ? input voltage operating range from 3.0 to 6.0 v ? 1% accurate output voltage, ranging from 0.7 to 3.6 v ? voltage tracking capability in different configurations. ? programmable switching frequency range from 200 khz to 1.0 mhz with a default of 1.0 mhz ? programmable soft start timing ? over-current limit and short-circuit protection ? thermal shutdown ? output over-voltage and under-voltage detection ? active low power good output signal ? active low shutdown input ? pb-free packaging designated by suffix code ep. figure 1. 34713 simplified application diagram switch-mode power supply ep suffix 98arl10577d 24-pin qfn 34713 ordering information device temperature range (t a ) package mc34713ep/r2 -40 to 85c 24 qfn vin vrefin pgnd vddi freq ilim gnd pvin boot sw inv comp vout pg sd 34713 vin v out v master (3.0 to 6.0 v) vin microcontroller dsp, fpga, asic
analog integrated circuit device data 2 freescale semiconductor 34713 internal block diagram internal block diagram figure 2. 34713 simplifi ed internal block diagram + ? + ? thermal monitoring system reset m1 discharge i limit system control internal voltage regulator v ddi m2 m3 m4 m5 v bg reference selection ramp generator v bg v ddi bandgap regulator discharge error amplifier pwm comparator prog soft start i sense i limit prog frequency oscillator current monitoring buck control logic gate driver f sw i sense v in v boot sd vin boot pvin sw pgnd comp inv vout gnd vrefin vddi ilim freq pg
analog integrated circuit device data freescale semiconductor 3 34713 pin connections pin connections figure 3. 34713 pin connections table 1. 34713 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 10 . pin number pin name pin function formal name definition 1 gnd ground signal ground analog signal ground of ic 2 freq passive frequency adjustment buck converter switching frequency adjustment pin 3 ilim input soft start soft start adjustment 4 pg output power good active-low (open drain) power-good status reporting pin 5, 8 nc none no connect no internal connections to thes e pins. recommend attaching a 0.1 f capacitor from pin 8 to gnd. 6 s d input shutdown shutdown mode input control pin 7 vrefin input voltage tracking reference input voltage tracking reference voltage input 9 comp passive compensation buck converter external compensation network pin 10 inv input error amplifier inverting input buck converter error amplifier inverting input pin 11 vout output output voltage discharge fet discharge fet drain connection (connect to buck converter output capacitors) 12,13,14 pgnd ground power ground ground return for buck converter and discharge fet 15,16,17 sw output switching node buck converter power switching node 18,19,20 pvin supply power-circuit supply input buck converter main supply voltage input 21 boot passive bootstrap bootstrap switching node (connect to bootstrap capacitor) 22,23 vin supply logic-circuit supply input logic circuits supply voltage input 24 vddi passive internal voltage regulator internal vdd regulator (connect fi lter capacitor to this pin) gnd freq ilim pg nc sd vrefin comp inv vout pgnd sw pvin boot vin vddi nc pgnd pgnd sw sw pvin pvin vin transparent top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pin 25
analog integrated circuit device data 4 freescale semiconductor 34713 pin connections 25 gnd ground thermal pad thermal pad for heat transfer. connect the thermal pad to the analog ground and the ground plane for heat sinking. table 1. 34713 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 10 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 34713 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings input supply voltage (vin) pin v in -0.3 to 7.0 v high side mosfet drain voltage (pvin) pin pv in -0.3 to 7.0 v switching node (sw) pin v sw -0.3 to 7.0 v boot pin (referenced to sw pin) v boot - v sw -0.3 to 7.0 v pg , vout,and sd pins - -0.3 to 7.0 v vddi, freq, ilim, inv, comp, and vrefin pins - -0.3 to 3.0 v continuous output current (1) i out +5.0 a esd voltage (2) human body model machine model (mm) charge device model v esd1 v esd2 v esd3 2000 200 750 v thermal ratings operating ambient temperature (3) t a -40 to 85 c storage temperature t stg -65 to +150 c peak package reflow temperature during reflow (4) , (5) t pprt note 5 c maximum junction temperature t j(max) +150 c power dissipation (t a = 85c) (6) p d 2.9 w notes 1. continuous output current capability so long as t j is t j(max) . 2. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ), the machine model (mm) (c zap = 200 pf, r zap = 0 ), and the charge device model (cdm), robotic (c zap = 4.0 pf). 3. the limiting factor is junction temperature, taking into account power dissipation, ther mal resistance, and heatsinking. 4. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. 6. maximum power dissipation at indicated ambient temperature
analog integrated circuit device data 6 freescale semiconductor 34713 electrical characteristics maximum ratings thermal resistance (7) thermal resistance, junction to ambient, single-layer board (1s) (8) r ja 139 c/w thermal resistance, junction to ambient, four-layer board (2s2p) (9) r jma 43 c/w thermal resistance, junction to board (10) r jb 22 c/w notes 7. the pvin, sw, and pgnd pins comprise the main heat conduction paths. 8. per semi g38-87 and jedec jesd51-2 with th e single-layer board (jesd51-3) horizontal. 9. per jedec jesd51-6 with the board (jesd51-7) horizontal. ther e are no thermal vias connecting the package to the two planes i n the board. 10. thermal resistance between the device and the printed circuit board per jedec jesd51- 8. board temperature is measured on the top surface of the board near the package. table 2. maximum ratings (continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data freescale semiconductor 7 34713 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit ic input supply voltage (vin) input supply voltage operating range v in 3.0 - 6.0 v input dc supply current (11) normal mode: sd = 1, unloaded outputs i in - - 25 ma input dc supply current (11) shutdown mode, sd = 0 i inoff - - 100 a internal supply voltage output (vddi) internal supply voltage range v ddi 2.35 2.5 2.65 v buck converter (pvin, sw, pgnd, boot, inv, comp, ilim) high side mosfet drain voltage range p vin 2.5 - 6.0 v output voltage adjustment range (12),(13) v out 0.7 - 3.6 v output voltage accuracy (12) , (14) - -1.0 - 1.0 % line regulation (12) normal operation, v in = 3.0 to 6.0 v, i out = +5.0 a reg ln -1.0 - 1.0 % load regulation (12) normal operation, i out = 0.0 to 5.0 a reg ld -1.0 - 1.0 % error amplifier common mode voltage range (12),(13) v ref 0.0 - 1.35 v output under-voltage threshold v uvr -8.0 - -1.5 % output over-voltage threshold v ovr 1.5 - 8.0 % continuous output current i out - - 5.0 a over-current limit i lim - 6.5 - a soft start adjusting reference voltage range v ilim 1.25 - v ddi v short-circuit current limit i short - 8.5 - a high side n-ch power mosfet (m3) r ds(on) (12) i out = 1.0 a, v boot - v sw = 3.3 v r ds(on)hs 10 - 50 m low side n-ch power mosfet (m4) r ds(on) (12) i out = 1.0 a, v in = 3.3 v r ds(on)ls 10 - 50 m notes 11. section ?modes of operation?, page 13 has a detailed description of the different operating modes of the 34713 12. design information only, this parameter is not production tested. 13. the 1% accuracy is only guaranteed for vefout greater then or equal 0.7 v at room temperature. 14. overall output accuracy is directly affected by the accura cy of the external feedback network, 1% feedback resistors are rec ommended
analog integrated circuit device data 8 freescale semiconductor 34713 electrical characteristics static electrical characteristics m2 r ds(on) v in = 3.3 v, m2 is on r ds(on)m2 1.5 - 4.0 sw leakage current (standby and shutdown modes) i sw -10 - 10 a pvin pin leakage current shutdown mode i pvin -10 - 10 a inv pin leakage current i inv -1.0 - 1.0 a error amplifier dc gain (15) a ea - 150 - db error amplifier unit gain bandwidth (15) ugbw ea - 3.0 - mhz error amplifier slew rate (15) sr ea - 7.0 - v/s error amplifier input offset (15) offset ea -3.0 0 3.0 mv thermal shutdown threshold (15) t sdfet - 170 - c thermal shutdown hysteresis (15) t sdhyfet - 25 - c oscillator (freq) oscillator frequency adjusting reference voltage range v freq 0.0 - v ddi v tracking (vrefin, vout) vrefin external reference voltage range (15) v refin 0.0 - 1.35 v vout total discharge resistance (15) r tdr(m5) - 50 - control and supervisory ( sd , pg ) sd high level input voltage v sdhi 2.0 - - v sd low level input voltage v sdlo - - 0.4 v sd pin internal pull-up resistor (15) r sdup 1.0 - 2.0 m pg low level output voltage i pg = 3.0 ma v pglo - - 0.4 v pg pin leakage current m1 is off, pulled up to vin i pglkg -1.0 - 1.0 a notes 15. design information only, this parameter is not production tested. table 3. static elec trical characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 34713 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit buck converter (pvin, sw, pgnd, boot) switching node (sw) rise time (16) (p vin = 3.3 v, i out = 5.0 a) t rise - 14 - ns switching node (sw) fall time (16) (p vin = 3.3 v, i out = 5.0 a) t fall - 20 - ns minimum off time t offmin - 150 - ns minimum on time t onmin - 0 (17) - ns soft start duration (normal mode) ilim= 1.25 - 1.49 v 1.50 - 1.81 v 1.82 - 2.13 v 2.14 - 2.50 v t ss - - - - 3.2 1.6 0.8 0.4 - - - - ms over-current limit timer t lim - 10 - ms over-current limit retry time-out period t timeout 80 - 120 ms output under-voltage/over-voltage filter delay timer t filter 5.0 - 25 s oscillator (freq) oscillator default switching frequency oscillator frequency toleranc e is 10% (freq = gnd) f sw - 1.0 - mhz oscillator switching frequency range f sw 200 - 1000 khz control and supervisory ( sd , pg ) pg reset delay t pgreset 8.0 - 12 ms thermal shutdown retry timeout period (16) t timeout 80 - 120 ms notes 16. design information only, this parameter is not production tested. 17. the regulator has the ability to enter into pulse skip mode when the inductor current ripple reaches the threshold for the l s zero detect, which has a typical value of 500 ma.
analog integrated circuit device data 10 freescale semiconductor 34713 functional description introduction functional description introduction advanced microprocessor-based systems require compact, efficient, and accurate point-of-load (pol) power supplies. these pol supply high current and fast transient response capability while maintaining regulation accuracy. voltage monitoring (power sequencing) and increased operating frequency are also key features for pol power supplies. pol power supplies are non-isolated dc to dc converters that are physically located near their load (on the same printed circuit board) and take their input supply from an intermediate bus. their close prox imity to the load allows for higher efficiency, localize d protection, and minimum distribution losses. their compact design and low component-count also reduces overall system cost. the 34713 is a pol single-output power supply that embodies an integrated solution that?s both highly cost- effective and reliable. it ut ilizes a voltage-mode synchronous buck switching converter topology with integrated low r ds(on) (50 m ) n-channel power mosfets for high- efficiency operation. it provid es an output voltage with an accuracy of less than 2.0%, capable of supplying up to 5.0 a of continuous current. its power sequencing/tracking abilities makes it ideal for systems with multiple related supply rails. it has an adjustable switching frequency, thus permitting greater design flexibility and optimization over a wide range of operating conditions, a nd can operate at up to 1.0 mhz to significantly reduce the external components size and cost. it also features an over-current limit control, and protects against output over-voltage, under-voltage, and over- temperature conditions. it al so protects the system from short-circuit events and incor porates a power-good output signal to alert the host mcu should a fault occur. operation can be enabled or disabled by controlling the sd pin, which offers power sequencing capabilities. by monolithically integrati ng the control and supervisory circuitry along with power-fets, the 34713 offers a complete, compact, cost-effective, and si mple solution to satisfy the pol needs of today?s systems. functional pin description reference voltage input (vrefin) the 34713 will track the voltage applied at this pin. frequency adjustment input (freq) the buck converter switching frequency can be adjusted by connecting this pin to an ex ternal resistor divider between vddi and gnd pins. the defau lt switching frequency (freq pin connected to ground, gnd) is set at 1.0 mhz. soft start adjustment input (ilim) soft start timing can be adjusted by applying an external voltage between 1.25 v and v ddi on this pin. signal ground (gnd) analog ground of the ic. internal analog signals are referenced to this pin voltage. internal supply voltage output (vddi) this is the output of the internal bias voltage regulator. connect a 1.0 f, 6.0 v low esr ceramic filter capacitor between this pin and the gnd pin. filtering any spikes on this output is essential to the inte rnal circuitry stable operation. output voltage disc harge path (vout) output voltage of the buck conv erter is connected to this pin. it only serves as the output discharge path once the sd signal is asserted. error amplifier inverting input (inv) buck converter error amplifier inverting input. connect the output voltage feedback network to this pin. compensation input (comp) buck converter external compensation network connects to this pin. use a type iii compensation network. input supply voltage (vin) ic power supply input voltage. input filtering is required for the device to operate properly. power ground (pgnd) buck converter and discharge mosfet power ground. it is the source of the buck converter low side power mosfet. switching node (sw) buck converter switching node. this pin is connected to the output inductor. power input voltage (pvin) buck converter power input voltage. this is the drain of the buck converter high side power mosfet. bootstrap input (boot) bootstrap capacitor input pin. connect a capacitor (as discussed on page 18 ) between this pin and the sw pin to
analog integrated circuit device data freescale semiconductor 11 34713 functional description functional internal block description enhance the gate of the high side power mosfet during switching. shutdown input ( sd ) if this pin is tied to the gnd pin, the device will be in shutdown mode. if left unconnected or tied to the vin pin, the device will be in normal mode. the pin has an internal pull- up of 1.5 m . power good output signal ( pg ) this is an active low open drain output that is used to report the status of the device to a host. this output activates after a successful power up sequence and stays active as long as the device is in normal operation and is not experiencing any faults. this output activates after a 10 ms delay and must be pulled up by an external resistor to a supply voltage (e.g., v in ). functional internal block description figure 4. 34713 block diagram internal bias circuits this block contains all circui ts that provide the necessary supply voltages and bias currents for the internal circuitry. it consists of: ? internal voltage supply regulator: this regulator supplies the v ddi voltage that is used to drive the digital/ analog internal circuits. it is equipped with a power-on- reset (por) circuit that watc hes for the right regulation levels. external filtering is needed on the vddi pin. this block will turn off during the shutdown mode. ? internal bandgap reference voltage: this supplies the reference voltage to some of the internal circuitry. ? bias circuit: this block generates the bias currents necessary to run all of the blocks in the ic. system control and logic this block is the brain of the ic where the device processes data and reacts to it . based on the status of the sd pin, the system control reacts accordingly and orders the device into the right status. it al so takes inputs from all of the monitoring/protection circuits and initiates power up or power down commands. it communicates with the buck converter to manage the switching operation and protects it against any faults. oscillator this block generate s the clock cycles necessary to run the ic digital blocks. it also generates the buck converter switching frequency. the switching frequency has a default value of 1.0 mhz and can be programmed by connecting a resistor divider to the freq pin, between vddi and gnd pins (see figure 1 ). protection functions this block contains the following circuits: ? over-current limit and short-circuit detection: this block monitors the output of the buck converter for over current conditions and short-circuit events and alerts the system control fo r further command. ? thermal limit detection: this block monitors the temperature of the device for overheating events. if the temperature rises abov e the thermal shutdown mc34713 - functional block diagram internal bias circuits system control and logic oscillator protection functions control and supervisory functions tracking and sequencing buck converter
analog integrated circuit device data 12 freescale semiconductor 34713 functional description functional internal block description threshold, this block will alert the system control for further commands. ? output over-voltage and under-voltage monitoring: this block monitors the buck c onverter output voltage to ensure it is within regulation boundaries. if not, this block alerts the system c ontrol for further commands. control and supervi sory functions this block is used to interface with an outside host. it contains the following circuits: ? shutdown control input: an outside host can put the 34713 device into shutdown mode by sending a logic ?0? to the sd pin. ? power good output signal pg : the 34713 can communicate to an external host that a fault has occurred by releasing the drive on the pg pin high, allowing the signal/pin to be pulled high by the external pull-up resistor. tracking and sequencing this block allows the output of the 34713 to track the voltage applied at the vrefin pin in different tracking configurations. this will be discussed in further details later in this document. for power down during a shutdown mode, the 34713 uses internal discharge mosfet ( figure 2 ) to discharge the output. the discharge mosfet is only active during shutdown mode. using this block along with controlling the sd pin can offer the user power sequencing capabilities by controlling when to turn the 34713 output on or off. buck converter this block provides the main function of the 34713: dc to dc conversion from an un-regulated input voltage to a regulated output voltage used by the loads for reliable operation. the buck converter is a high performance, fixed frequency (externally adjustable), synchronous buck pwm voltage-mode control. it drives integrated 50 m n-channel power mosfets saving board space and enhancing efficiency. the switching regulator output voltage is adjustable with an accuracy of less than 2% to meet today?s requirements. its output has th e ability to track the voltage applied at the vrefin pin. the regulator's voltage control loop is compensated using a type iii compensation network, with external components to allow for optimizing the loop compensation, for a wide range of operating conditions. a typical bootstrap circuit with an in ternal pmos switch is used to provide the voltage necessary to properly enhance the high side mosfet gate. the 34713 has the ability to supply up to 5.0 a of continuous current, making it suitable for many high current applications.
analog integrated circuit device data freescale semiconductor 13 34713 functional device operation operational modes functional device operation operational modes figure 5. operation modes diagram modes of operation the 34713 has two primary modes of operation: normal mode in normal mode, all functions and outputs are fully operational. to be in this mode, the v in needs to be within its operating range, shutdown input is high, and no faults are present. this mode consumes the most amount of power. shutdown mode in this mode, activated by pulling the sd pin low, the chip is in a shutdown state and the output is disabled and discharged. in this mode, t he 34713 consumes the least amount of power since almost al l of the internal blocks are disabled. start-up sequence when power is first applied, the 34713 checks the status of the sd pin. if the device is in a shutdown mode, no block will power up and the output will not attempt to ramp. once the sd pin is released to enable the device, the v ddi internal supply voltage and the bias cu rrents are established and the internal v ddi por signal is also released. the rest of the internal blocks will be enabled and the buck converter switching frequency and soft st art values are determined by reading the freq and ilim pins respectively. a soft start cycle is then initiate d to ramp up the output of the buck converter. the buck converter error amplifier uses the voltage on the vrefin pin as its reference voltage until v refin is equal to 0.7 v, then the error amplifier defaults to the internal 0.7 v reference voltage. this method helps achieve multiple tracking configurations as will be explained later in this document. soft start is used to prev ent the output voltage from overshooting during startup. at initial startup, the output capacitor is at zero volts; v out = 0 v. therefore, the voltage across the inductor will be pv in during the capacitor charge phase which will create a very sharp di/dt ramp. allowing the inductor current to rise too high can result in a large difference between the charging current and the actual load current that can result in an undesired voltage spike once the capacitor is fully charged. the so ft start is active each time the ic goes out of standby or shutdown mode, power is recycled, or afte r a fault retry. after a successful start-up cycle where the device is enabled, no faults have occurr ed, and the output voltage has reached its regulation point, the 34713 pulls the power good normal v tt = on pg = 0 shutdown v out = discharge v ref = discharge pg = 1 v in < 3.0 v i out >=i short i out1 >=i lim1 for>=10 ms t j >= 170 c v out >v ov 3.0 v<=v in <=6.0 v t j <=145 c t imeout expired t imeout expired v out v uv
analog integrated circuit device data 14 freescale semiconductor 34713 functional device operation protection and di agnostic features output signal low after a 10 ms reset delay, to indicate to the host that the device is in normal operation. protection and diagnostic features the 34713 monitors the application for several fault conditions to protect the load fr om overstress. the reaction of the ic to these faults ranges from turning off the outputs to just alerting the host that something is wrong. in the following paragraphs, each fault c ondition is explained: output over-voltage an over-voltage condition occurs once the output voltage goes higher than the rising over-voltage threshold (v ovr ). in this case, the power good output signal is pulled high, alerting the host that a fault is present, but the output will stay active. to avoid erroneous over-voltage conditions, a 20 s filter is implemented. the buck converter will use its feedback loop to attempt to correct the fault. once the output voltage falls below the falling over-voltage threshold (v ovf ), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. output under-voltage an under-voltage condition o ccurs once the output voltage falls below the falling under-voltage threshold (v uvf ). in this case, the power good output signal is pulled high, alerting the host that a fault is present, bu t the output will st ay active. to avoid erroneous under-voltage conditions, a 20 s filter is implemented. the buck converter will use its feedback loop to attempt to correct the fault. once the output voltage rises above the rising under-voltage threshold (v uvr ), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. output over-current this block detects over-curre nt in the power mosfets of the buck converter. it is co mprised of a sense mosfet and a comparator. the sense mosfet acts as a current detecting device by sampling a ratio of the load current. that sample is compared via the comparator with an internal reference to determine if the output is in over-current or not. if the peak current in the outpu t inductor reaches the over current limit (i lim ), the converter will start a cycle-by-cycle operation to limit the current, and a 10 ms over-current limit timer (t lim ) starts. the converter will stay in this mode of operation until one of the following occurs: ? the current is reduced back to the normal level before t lim expires, and in this case normal operation is regained. ?t lim expires without regaining normal operation, at which point the device turns off the output and the power good output signal is pulled high. at the end of a time-out period of 100 ms (t timeout ), the device will attempt another soft start cycle. ? the device reaches the thermal shutdown limit (t sdfet ) and turns off the output. the power good output signal is pulled high. ? the output current keeps increasing until it reaches the short circuit current limit (i short ). see below for more details. short-circuit current limit this block uses the same cu rrent detection mechanism as the over-current limit detection block. if the load current reaches the i short value, the device reacts by shutting down the output immediately. this is necessary to prevent damage in case of a permanent short-ci rcuit. then, at the end of a timeout period of 100 ms (t timeout ), the device will attempt another soft start cycle. thermal shutdown thermal limit detection block monitors the te mperature of the device and protects agains t excessive heat ing. if the temperature reaches the thermal shutdown threshold (t sdfet ), the converter output switches off and the power good output signal indicates a fault by pulling high. the device will stay in this st ate until the temperature has decreased by the hysteresis value and then after a timeout period (t timeout ) of 100 ms, the device will retry automatically and the output will go through a soft start cycle. if successful normal operation is regained, the power good output signal is asserted low to indicate that.
analog integrated circuit device data freescale semiconductor 15 34713 typical applications typical applications figure 6. typical applications sgnd ilim nc gnd vout vrefin nc sd comp inv vout gnd sw sw pvin pvin pvin pvin pvin boot vddi vin vin 0.1 f c14 vddi inv comp 0.1 f c15 boot x r10 vin freq ilim freq 0.1 f c12 0.1 f c11 pg sd mc34713 1 2 3 5 6 78 91011 13 12 14 17 18 19 20 21 22 23 24 4 15 16 c18 0.02 pf r15 15 k c19 1.9 nf r2 12.7 k c20 0.910 nf r14 300 r1 20 k comp vout inv compensation network buck converter vout c8 100 f c7 100 f c6 100 f r3 4.7_nopop c9 1n f_nopop d3 pmeg2010ea _nopop l1 1.5 h sw vout1 vout2 0.1 f c13 vrefin gnd gnd sw sw sw pg 10 k r13 10 k_nopop r12 10 k_nopop r11 10 k j2 j3 pvin vin gnd 3 2 1 3 2 1 gnd vout vmaster i/o signals r16 4.7_nopop vmaster vrefin r8 10 k r9 10 k vmaster r7 1k d1 led vin led pgood led stby_nopop pvin vmaster led vrefin pg sd j1 sd con10a 1 1 1 2 2 2 3 4 56 7 8 9 10 jumpers x pvin c1 0.1 f c2 1 .0 f c3 100 f c4 100 f c5 100 f pvin capacitors vin c17 10 f c16 0.1 f vin capacitors vddi r5 pot_50 k_nopop r6 pot_50 k_nopop ilim freq optional nopop sw
analog integrated circuit device data 16 freescale semiconductor 34713 typical applications component selection switching frequency selection the switching frequency defaults to a value of 1.0 mhz when the freq pin is grounded, and 200 khz when the freq pin is connected to vddi. intermediate switching frequencies can be obtained by connecting an external resistor divider to the freq pin. the table below shows the resulting switching frequency versus freq pin voltage. table 5. switching frequency adjustment figure 7. resistor divider for frequency adjustment selection of the inductor inductor calculation is straight forward, being where, maximum off time percentage switching period. drain ? to ? source resistance of fet winding resistan ce of inductor output current ripple. output filter capacitor for the output capacitor, the following considerations are more important than the act ual capacitance value, the physical size, the esr and the voltage rating: transient response percentage, tr_% (use a recommended value of 2 to 4% to assure a good transient response.) maximum transient voltage, tr_v_dip = vo*tr_% maximum current step, inductor current rise time, where, d_max = maximum on time percentage. i o = rated output current. vin_min = minimum input voltage at pv in as a result, it is possible to calculate frequency voltage applied to pin freq 200 2.341 ? 2.500 253 2.185 - 2.340 307 2.029 - 2.184 360 1.873 - 2.028 413 1.717 ? 1.872 466 1.561 ? 1.716 520 1.405 - 1.560 573 1.249 - 1.404 627 1.093 - 1.248 680 0.936 - 1.092 733 0.781 - 0.936 787 0.625 - 0.780 840 0.469 - 0.624 893 0.313 - 0.468 947 0.157 - 0.312 1000 0.000 - 0.156 r fqh r fql vddi freq gnd
analog integrated circuit device data freescale semiconductor 17 34713 typical applications in order to find the maximum allowed esr, the effects of the esr is ofte n neglected by the designers and may present a hidden danger to the ultimate supply stability. poor quality capacitors have widely disparate esr value, which can make the closed loop response inconsistent. figure 8. transient parameters type iii compensation network power supplies are desired to offer accurate and tight regulation output voltages. to accomplish this requires a high dc gain. but with high gain comes the possibility of instability. the purpose of adding compensation to the internal error amplifier is to counteract some of the gains and phases contained in the control-to-out put transfer function that could jeopardized the stability of the power supply. the type iii compensation network used for 34713 comprises two poles (one integrator and one high frequency pole to cancel the zero generated from the esr of the output capacitor) and two zeros to cancel the two poles generated from the lc filter as shown in figure 9 . figure 9. type iii compensation network consider the crossover frequency, f cross , of the open loop gain at one-tenth of the switching frequency, f sw. then, where r o is a user selected resistor. knowing the lc frequency, it can be obtained the values of r f and c s : this gives as a result, calculate rs by placing the pole 1 at the esr zero frequency: io worst case assumption current response dt_i_rise io_step + ? + ? f sw gate driver pwm comparitor v refin ramp generator error amplifier sw vout inv comp l r s c s r o c o c x r f c f boot c boot r b v ddi reference selection bandgap regulator 34713 v o v ref r o r b ------- 1 + ?? ?? = ? r o c f ? ---------------------------- = c f 10 2 r o f cross ? --------------------------------------- = &
analog integrated circuit device data 18 freescale semiconductor 34713 typical applications equating the pole 2 to 5 times the crossover frequency to achieve a faster response and a proper phase margin, bootstrap capacitor the bootstrap capacitor is needed to supply the gate voltage for the high side mosfet. this n-channel mosfet needs a voltage difference between its gate and source to be able to turn on. the high side mosfet source is the sw node, so it is not ground and it is floating and moving in voltage, so we cannot just appl y a voltage directly to the gate of the high side that is referenced to ground, we need a voltage referenced to the sw n ode. that is why the bootstrap capacitor is needed for. this capacitor charges during the high side off time, since the low side will be on during that time, so the sw node and the bottom of the bootstrap capacitor will be connected to ground and the top of the capacitor will be connected to a voltage source, so the capacitor will charge up to t hat voltage source (say 5.0 v). now when the low side mosfet switches off and the high side mosfet switches on, the sw nodes rises up to vin, and the voltage on the boot pin will be vcap + vin. so the gate of the high side will have vcap across it and it will be able to stay enhanced. a 0.1 f capacitor is a good value for this bootstrap element. layout guidelines the layout of any switching regulator requires careful consideration. first, there are high di/dt signals present, and the traces carrying these signal s need to be kept as short and as wide as possible to minimize the trace inductance, and therefore reduce the voltage spik es they can create. to do this, an understanding of the major current carrying loops is important. see figure 10 . these loops, and their associated components, should be placed in such a way as to minimize the loop size to prevent coupling to other parts of the circuit. also, the current carrying power traces and their associated return traces should run adjacent to one another, to minimize the amount of noise coupling. if sensitive traces must cross the current carrying traces, they should be made perpendicular to one another to reduce field interaction . second, small signal components which connect to sensitive nodes need considerati on. the critical small signal components are the ones associated with the feedback circuit. the high impedance input of the error amp is especially sensitive to noise, and the feedback and compensation components should be placed as far from the switch node, and as close to the input of the error amplifier as possible. other critical small signal components include the bypass capacitors for vin, vr efin, and vddi. locate the bypass capacitors as close to the pin as possible. the use of a multi-layer printed circuit board is recommended. dedicate one layer, usually the layer under the top layer, as a ground plane. make all critical component ground connections with vias to th is layer. make sure that the power ground, pgnd, is connec ted directly to the ground plane and not routed through the thermal pad or analog ground. dedicate another layer as a power plane and split this plane into local areas for common voltage nets. the ic input supply (vin) should be connected with a dedicated trace to the input s upply. this will help prevent noise from the buck regulator's power input (pvin) from injecting switching noise into the ic?s analog circuitry. in order to effectively transfer heat from the top layer to the ground plane and other layers of the printed circuit board, thermal vias need to be used in the thermal pad design. it is recommended that 5 to 9 vias be spaced evenly and have a finished diameter of 0.3 mm. ? 5 f ? cross f p2 1 2 r f c f c x c f c x + -------------------- - ? ---------------------------------------- - == ?
analog integrated circuit device data freescale semiconductor 19 34713 typical applications figure 10. current loops soft start selection table 6 shows the voltage that should be applied to the terminal ilim to get the desired configuration of the soft start timing. vin1 buck con vert er 1 h s sd loop current sd on loop curr ent hs on vin2 and 3 buck converter 2 and 3 hs ls loop current ls on loop curr ent hs on sw1 sw2 and 3 gnd2 and 3 buck converter pgnd sw pvin table 6. ilim table soft start (ms) voltage applied to ilim 3.2 1.25 - 1.49 1.6 1.50 - 1.81 0.8 1.82 - 2.13 0.4 2.14 - 2.50
analog integrated circuit device data 20 freescale semiconductor 34713 packaging packaging dimensions packaging packaging dimensions ep suffix 24-pin 98arl10577d issue b
analog integrated circuit device data freescale semiconductor 21 34713 packaging packaging dimensions ep suffix 24-pin 98arl10577d issue b
analog integrated circuit device data 22 freescale semiconductor 34713 revision history revision history revision date description of changes 1.0 2/2006 ? pre-release version ? implemented revision history page 2.0 11/2006 ? initial release ? converted format from market assessment to product preview ? major updates to the data, form, and style 3.0 2/2007 ? major updates to the data, form, and style 4.0 5/2007 ? changed feature fom 2% to 1%, relabeled to include soft start ? changed 34713 simplified application diagram ? made change to 34713 simplified internal block diagram ? removed machine model in maximum ratings ? changed input dc supply current (11) normal mode and input dc supply current (11) shutdown mode ? changed output voltage accuracy (12) , (14) ? changed soft start adjusting reference voltage range and short-circuit current limit ? changed high side n-ch power mosfet (m3) rds(on) (12) and low side n-ch power mosfet (m4) rds(on) (12) ? changed m2 rds(on) and pvin pin leakage current ? changed sd pin internal pull-up resistor (15) ? changed changed soft start duration (normal mode) ? changed over-current limit retry time-out period and output under-voltage/over-voltage filter delay timer ? changed pg reset delay and thermal shutdown retry timeout period (16) ? changed definition for soft start adjustment input (ilim) ? changed drawings in typical applications ? changed drawing in type iii compensation network ? changed table for soft start selection ? removed pc34713ep/r2 from the ordering information and added mc34713ep/r2 ? changed the data sheet status to advance information 5.0 1/2008 ? made changes to switching node (sw) pin , boot pin (referenced to sw pin) , output under- voltage threshold , output over-voltage threshold , high side n-ch power mosfet (m3) rds(on) (12) , low side n-ch power mosfet (m4) rds(on) (12) , charge device model ? added machine model (mm) , sw leakage current (standby and shutdown modes) , error amplifier dc gain (15) , error amplifier unit gain bandwidth (15) , error amplifier slew rate (15) , error amplifier input offset (15) , high side mosfet drain voltage (pvin) pin ? added pin 25 to figure 3 and the 34713 pin definitions ? added the section layout guidelines
mc34713 rev. 5.0 12/2008 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007-8. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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